1 www.pericom.com 04/15/13 features ? 4 differential channel, 2:1 mux/demux ? pci express ? 3.0 performance, 8.0gbps ? bi-directional operation ? low bit-to-bit skew, 10ps max ? low channel-to-channel skew, 20ps max ? low crosstalk: -35db@4 ghz ? high off isolation: -22db@4 ghz (8.0gbps) ? low insertion loss: -1.3db@4 ghz (8.0gbps) ? return loss: -21db@4 ghz ? support for dp1.2 - hbr2, hbr, rbr ? supply v oltage 3.3v ? packaging (pb-free & green): C 42-contact, tqfn (zh42) description pericom semiconductor s PI3PCIE3412 is an 8 to 4 dif ferential channel multipl exer/demultiplexer switch. this solution can switch 2 full pci express ? 3.0, lanes to one of two locations. using a unique design techniq ue, pericom has been able to minimize the impedance of the switch such that the attenuation observed through the switch is mininal. the unique design technique also of fers a layout tar geted for pci express signals, which minimizes the channel to channel skew as well as channel to channel crosstalk as required by the pci express specifcation. PI3PCIE3412 can also be used for application up to 12gbps application routing of pci express 3.0, dp1.2, usb3.0, sas2.0, sa ta3.0, xaui, rxaui signals with low signal attenuation. block diagram pin confguration (top-side view) truth table function sel a n to b n l a n to c n h a1- a1+ a0- a0+ a3- a3+ a2- a2+ b0+ b0- b1+ b1- c0+ c0- c1+ c1- b2+ b2- b3+ b3- c2+ c2- c3+ c3- sel 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 42 41 40 39 18 19 20 21 v dd dng v dd dng v dd dng v dd dng b0+ b0- b1+ b1- c0+ c0- c1+ c1- v dd b2+ b2- b3+ b3- c2+ c2- c3+ c3- gnd a0+ a0- gnd v dd a1+ a1- v dd sel gnd a2+ a2- v dd gnd a3+ a3- gnd PI3PCIE3412 3.3v, pci express? 3.0 2-lane, 2:1 mux/demux switch, with single enable 13-0046
2 www.pericom.com 04/15/13 pin description pin # pin name i/o description 2 3 a0+ a0C i/o signal i/o, channel 0, port a 6 7 a1+ a1C i/o signal i/o, channel 1, port a 11 12 a2+ a2C i/o signal i/o, channel 2, port a 15 16 a3+ a3C i/o signal i/o, channel 3, port a 38 37 b0+ b0? i/o signal i/o, channel 0, port b 36 35 b1+ b1? i/o signal i/o, channel 1, port b 29 28 b2+ b2? i/o signal i/o, channel 2, port b 27 26 b3+ b3? i/o signal i/o, channel 3, port b 34 33 c0+ c0C i/o signal i/o, channel 0, port c 32 31 c1+ c1C i/o signal i/o, channel 1, port c 25 24 c2+ c2C i/o signal i/o, channel 2, port c 23 22 c3+ c3? i/o signal i/o, channel 3, port c 9 sel i operation mode select (when sel=0: ab, when sel=1: ac 5, 8, 13,18, 20, 30, 40, 42 v dd pwr 3.3v 10% positive supply voltage 1, 4, 10,14, 17, 19, 21, 39, 41, center pad gnd pwr power ground PI3PCIE3412 pci express? 3.0 2-lane, 2:1 mux/demux switch with single enable 13-0046
3 www.pericom.com 04/15/13 storage t emperature ....................................................C65c to +150c supply v oltage to ground potential ................................C0.5v to +4.6v channel dc input v oltage ................................................ C0.5v to 1.5v dc output current ....................................................................... 120ma power dissipation ........................................................................... 0.5w sel dc input v oltage ....................................................... C0.5v to 4.6v note: stresses greater than those listed under maximum ra tings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifca tion is not implied. expo - sure to absolute maximum rating conditions for extended periods may affect reliability. maximum ratings (above which useful life may be impaired. for user guidelines, not tested.) switching characteristics param - eters description test conditions min. ty p. max. units t pzh , t pzl line enable time - sel to a n , b n, c n 2 20 25 ns t phz , t plz line disable time - sel to a n , b n, c n 0.5 5 25 t b-b bit-to-bit skew within the same diferential pair 5 10 ps t ch-ch channel-to-channel skew 20 ps recommended operating conditions symbol parameter conditions min typ max units v dd 3.3v power supply 3.0 3.3 3.6 v i dd total current from v dd 3.3v supply sel = 0v or v dd 0.15 1 ma v i/o -dif differential v oltage (differential pins) 1.6 v ppd v i/o-cm common mode v oltage (differiential pins) 0 0.8 v t case case temperature range for operation within spec. -40 85 celsius electrical characteristics dc electrical characteristics for switching over operating range parameters description test conditions (1) min ty p (1) max units v ih - sel input high voltage, sel input 2 3.6 v v il - sel input low voltage, sel input 0 0.8 v ik clamp diode voltage v dd = max., i in = C18ma C0.7 C1.2 i ih input high current, sel v dd = max., v in = v dd 5 a i il input low current, sel v dd = max., v in = 0v 5 i in - sel input leakage current, sel input v in = v ih - sel max or v il - sel min C10 +10 a i ih input high current, a x , b x , c x v dd = max., v in = 1.5v C10 +10 a i il input low current, a x , b x , c x v dd = max., v in = 0v C10 +10 i ozh highz high current, b x , c x v dd = max., v in = 1.5v C10 +10 a i ozl highz low current, b x , c x v dd = max., v in = 0v C10 +10 a c i/o-on on state i/o capacitance 1.5 pf r on on state resistance v dd = 3.3v, io = 8ma, v in = 0.8v 5 note: 1. typical values are at v dd = 3.3v, t a = 25c ambient and maximum loading. PI3PCIE3412 pci express? 3.0 2-lane, 2:1 mux/demux switch with single enable 13-0046
4 www.pericom.com 04/15/13 dynamic electrical characteristics param - eter description test conditions min. ty p. (1) max. units ddil diferential insertion loss (v in = -10dbm, dc = 0v) f= 50mhz - 1.25ghz f=1.25ghz - 2.5ghz f=2.5ghz - 4ghz f=5ghz -0.8 -1.0 -1.3 -1.8 -1 -1.2 -1.6 -2.2 db ddil off diferential of isolation f= 50mhz - 1.25ghz f=1.25ghz - 2.5ghz f=2.5ghz - 4ghz f=5ghz -26.3 -21.4 -17.6 -16 -32.9 -26.7 -22 -20 db ddrl diferential return loss f= 50mhz - 1.25ghz f=1.25ghz - 2.5ghz f=2.5ghz - 4ghz f=5ghz -20 -18.4 -16.8 -9.6 -25 -23 -21 -12 db ddnext near end crosstalk f= 50mhz - 1.25ghz f=1.25ghz - 2.5ghz f=2.5ghz - 4ghz f=5ghz -34.1 -30.5 -28.1 -27.2 -42.6 -38.1 -35.1 -34 db v i f max signal frequency range insertion loss 1.5db, v in =0.623vpp, dc=0v 4.0 ghz insertion loss 1.5db, v in =0.623vpp, dc=0.9v 4.0 insertion loss 3db, v in =0.623vpp, dc=0v 8.0 insertion loss 3db, v in =0.623vpp, dc=0.9v 8.0 bw -3db bandwidth 8.2 ghz notes: 1. guaranteed by design. t ypical values are at v dd = 3.3v , t a = 25c ambient and maximum loading. + ? + ? balanced port1 dut + ? 50 50 + ? balanced port2 50 50 diff. near end xtalk test circuit + ? + ? balanced port1 balanced port2 dut + ? 50 50 diff. off isolation test circuit + ? + ? balanced port1 balanced port2 dut diff. insertion loss and return test circuit PI3PCIE3412 pci express? 3.0 2-lane, 2:1 mux/demux switch with single enable 13-0046
5 www.pericom.com 04/15/13 differential insertion loss differential return loss PI3PCIE3412 pci express? 3.0 2-lane, 2:1 mux/demux switch with single enable 13-0046
6 www.pericom.com 04/15/13 differential off isolation differential crosstalk PI3PCIE3412 pci express? 3.0 2-lane, 2:1 mux/demux switch with single enable 13-0046
7 www.pericom.com 04/15/13 5.0 gbps rx signal eye with PI3PCIE3412 5.0 gbps rx signal eye without PI3PCIE3412 8.0 gbps rx signal eye with PI3PCIE3412 8.0 gbps rx signal eye without PI3PCIE3412 PI3PCIE3412 pci express? 3.0 2-lane, 2:1 mux/demux switch with single enable 13-0046
8 www.pericom.com 04/15/13 switch positions test switch t plz , t pzl 3.0v t phz , t pzh gnd prop delay open switching waveforms voltage waveforms enable and disable times t plz v dd /2 v dd /2 v dd 1.5v 0v v ol 0.75v 0.75v t phz t pzl t pzh output 1 output 2 v ol 1.5v sel v ol + 0.15v 1.35v r t 4pf c l v dd v in v out 200-ohm 200-ohm 3.0v pulse generator d.u.t test circuit for electrical characteristics (1-5) notes: 1. c l = load capacitance: includes jig and probe capacitance. 2. r t = t ermination resistance: should be equal to z out of the pulse generator 3. output 1 is for an output with internal conditions such that the output is low except when disabled by the output control. output 2 is for an output with internal conditions such that the output is high except when disabled by the output control. 4. all input impulses are supplied by generators having the following characteristics: prr mhz, z o = 50?, t r 2.5ns, t f 2.5ns. 5. the outputs are measured one at a time with one transition per measurement. PI3PCIE3412 pci express? 3.0 2-lane, 2:1 mux/demux switch with single enable 13-0046
9 www.pericom.com 04/15/13 dp1.2 application 5 5 4 4 3 3 2 2 1 1 d d c c b b a a dp _l anex dp _l anex# dp_hpd dp_aux dp_aux# dp_aux# dp_aux aux_p1 aux_p2 aux_n1 aux_n2 hpd1 hpd2 dp_hpd hpd1 hpd2 aux_n1 aux_p1 aux_p2 aux_n2 3v 3_1 3v 3_1 vbias_tx 3v 3_1 3v 3_1 3v 3_1 3v 3_1 5v_1 vbias_tx sel_ gpio1 title size docum ent num ber rev date: s heet of a pi3pcie 3412 4lane edp 1:2 a ppli cati on circui t with 0-1.2vbias 1 4 t ues day , march 06, 2012 title size docum ent num ber rev date: s heet of a pi3pcie 3412 4lane edp 1:2 a ppli cati on circui t with 0-1.2vbias 1 4 t ues day , march 06, 2012 title size docum ent num ber rev date: s heet of a pi3pcie 3412 4lane edp 1:2 a ppli cati on circui t with 0-1.2vbias 1 4 t ues day , march 06, 2012 same goes for other 3 lane s (0 - 1.2v) dp source 1 dp tx at least 1pc 4.7uf and 4pc 0.1u f decoupling capacitors ar e recommended . each decoupling capacitor shoul d be connected to pcb power plan e via shortest path . vdd and gnd pins should b e shorted to pcb power plane s via shortest paths . (0 - 1.2v) aux tx aux rx 5v_1 and 3v3_1 should b e employed at the same time . c12 3 0. 1u_0402 c12 3 0. 1u_0402 c13 0 0. 1u_0402 c13 0 0. 1u_0402 c12 2 0. 1u_0402 c12 2 0. 1u_0402 nc 1 h_gnd 2 lane3_n 3 lane3_p 4 h_gnd 5 lane2_n 6 lane2_p 7 h_gnd 8 lane1_n 9 lane1_p 10 h_gnd 11 lane0_n 12 h_gnd 14 lane0_p 13 aux_ ch_p 15 lcd _vcc 19 h_gnd 17 lcd _vcc 18 lcd _vcc 20 aux_ ch_n 16 lcd _vcc 21 lcd _self_test 22 lcd _gnd 23 lcd _gnd 24 lcd _gnd 25 lcd _gnd 26 hpd 27 bl_gnd 28 bl_gnd 29 bl_gnd 30 bl_gnd 31 bl_en able 32 bl_pwm_dim 33 nc 34 nc 35 bl_pwr 36 bl_pwr 37 bl_pwr 38 bl_pwr 39 nc 40 j 102 4lane edp s ou rce rec ep tacle j 102 4lane edp s ou rce rec ep tacle 50 50 c12 6 0. 1u_0402 c12 6 0. 1u_0402 c12 1 0. 1u_0402 c12 1 0. 1u_0402 c12 5 0. 1u_0402 c12 5 0. 1u_0402 c11 1 0. 1u_0402 c11 1 0. 1u_0402 c104 0. 1u_0402 c104 0. 1u_0402 c108 1u_0805 c108 1u_0805 c103 0. 1u_0402 c103 0. 1u_0402 c102 1u_0805 c102 1u_0805 in 1 s1a 2 s2a 3 da 4 s1b 5 s2b 6 db 7 gnd 8 dc 9 s2c 10 s1c 11 dd 12 s2d 13 s1d 14 #en 15 vdd 16 u102 pi5v 330 u102 pi5v 330 c11 0 0. 1u_0402 c11 0 0. 1u_0402 nc 1 h_gnd 2 lane3_n 3 lane3_p 4 h_gnd 5 lane2_n 6 lane2_p 7 h_gnd 8 lane1_n 9 lane1_p 10 h_gnd 11 lane0_n 12 h_gnd 14 lane0_p 13 aux_ ch_p 15 lcd _vcc 19 h_gnd 17 lcd _vcc 18 lcd _vcc 20 aux_ ch_n 16 lcd _vcc 21 lcd _self_test 22 lcd _gnd 23 lcd _gnd 24 lcd _gnd 25 lcd _gnd 26 hpd 27 bl_gnd 28 bl_gnd 29 bl_gnd 30 bl_gnd 31 bl_en able 32 bl_pwm_dim 33 nc 34 nc 35 bl_pwr 36 bl_pwr 37 bl_pwr 38 bl_pwr 39 nc 40 j 101 4lane edp s ou rce rec ep tacle j 101 4lane edp s ou rce rec ep tacle c10 9 0. 1u_0402 c10 9 0. 1u_0402 c12 7 0. 1u_0402 c12 7 0. 1u_0402 c12 4 0. 1u_0402 c12 4 0. 1u_0402 c12 9 0. 1u_0402 c12 9 0. 1u_0402 c11 8 0. 1u_0402 c11 8 0. 1u_0402 c101 4. 7u_0805 c101 4. 7u_0805 c120 1u_0805 c120 1u_0805 c11 7 0. 1u_0402 c11 7 0. 1u_0402 c11 2 0. 1u_0402 c11 2 0. 1u_0402 50 50 a3+ 15 a3- 16 gnd 17 vdd 18 gnd 19 vdd 20 gnd 21 c3- 22 c3+ 23 c2- 24 c2+ 25 b3- 26 b3+ 27 b2- 28 b2+ 29 vdd 30 c1- 31 c1+ 32 c0- 33 c0+ 34 b1- 35 b1+ 36 b0- 37 b0+ 38 gnd 39 vdd 40 gnd 41 vdd 42 gnd 1 a0+ 2 a0- 3 h ea tgnd 43 gnd 4 vdd 5 a1+ 6 a1- 7 vdd 8 sel 9 gnd 10 a2+ 11 a2- 12 vdd 13 gnd 14 u101 pi3pcie 3412 u101 pi3pcie 3412 c11 6 0. 1u_0402 c11 6 0. 1u_0402 c10 7 0. 1u_0402 c10 7 0. 1u_0402 c106 0. 1u_0402 c106 0. 1u_0402 c13 1 0. 1u_0402 c13 1 0. 1u_0402 c11 5 0. 1u_0402 c11 5 0. 1u_0402 50 50 c11 4 0. 1u_0402 c11 4 0. 1u_0402 c105 0. 1u_0402 c105 0. 1u_0402 c12 8 0. 1u_0402 c12 8 0. 1u_0402 c11 9 0. 1u_0402 c11 9 0. 1u_0402 50 50 c11 3 0. 1u_0402 c11 3 0. 1u_0402 PI3PCIE3412 pci express? 3.0 2-lane, 2:1 mux/demux switch with single enable 13-0046
10 www.pericom.com 04/15/13 ordering information ordering code package code package description PI3PCIE3412zhe zh pb-free & green, 42-contact tqfn notes: ? thermal characteristics can be found on the company web site at www.pericom.com/packaging/ ? "e" denotes pb-free and green ? adding an "x" at the end of the ordering code denotes tape and reel packaging pericom semiconductor corporation ? 1-800-435-2336 ? www .pericom.com date: 11/14/12 description: 42-contact thin fine pitch quad flat no-lead (tqfn) package code: zh42 document control #: pd-2035 revision:d notes: 1. all dimensions are in millimeters. angles in degrees. 2. coplanarity applies to the exposed pad as well as the terminals. 3. refer jedec mo-220. 4. recommended land pattern is for reference only. 5. thermal pad soldering area 12-0529 all trademarks are property of their respective owners. note: ? for latest package info, please check: http://www.pericom.com/products/packaging/mechanicals.php packaging information PI3PCIE3412 pci express? 3.0 2-lane, 2:1 mux/demux switch with single enable 13-0046
|
